Summary
According to a post on X by @dnystedt, Intel says its EMIB packaging uses more than 90% of each silicon wafer, compared with about 60% for interposer designs. Packaging director Kyu-oh Lee, speaking at ISMP in Busan, outlined a roadmap to 240×240mm packages with 32+ HBM stacks and 70+ EMIB bridges. The current figures cited are 120×120mm packages, 12 HBM stacks and 20+ bridges. The post says media reports suggest Google's TPU v9 and Amazon custom chips may adopt EMIB-T, but the snippet does not confirm this.
AI-assisted summary based on the listed source.
What happened
Intel says its EMIB packaging uses more than 90% of each silicon wafer versus about 60% for interposer designs, citing packaging director Kyu-oh Lee at ISMP in Busan. Lee sketched a roadmap to 240×240mm packages, 32+ HBM stacks, and 70+ EMIB bridges, up from 120×120mm, 12 HBM stacks, and 20+ bridges now. Media say...
Why it matters
Chip designers and packaging suppliers building larger AI packages with more memory stacks would be affected if Intel's roadmap is delivered. The wafer-use and package-size figures are Intel's own claims, and the possible TPU and Amazon adoption is only media reporting so far. Watch for confirmed customer announcements and product details for EMIB-T.
What this means for you
Hardware and robotics watchers may want to track whether this becomes a product, benchmark, or deployment signal.
Signal Intelligence
Signal Strength 94%
Technical label WATCH
Public Interest 45
Category ROBOTS & HARDWARE
Reader Depth TECHNICAL
Signal Strength reflects source quality, relevance, freshness and evidence. Public Interest helps organize discovery; it is not proof of truth.
Public Interest components
Recognizable Entity Score 82
Practical Impact Score 0
Novelty Interest Score 70
Consequence Score 30
Curiosity Score 0
Shareability Score 59
Why this is here
VQV surfaced this signal because it is recent, relevant to AI Chips, connected to Scobleizer News Pulse (X).
