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Novel Low-Power Circuit-Switched NoC Design for AI Chips
Researchers propose a new low-power circuit-switched network-on-chip (NoC) design that leverages predictable inter-core traffic in AI chips and multicore systems-on-chip. This design aims to optimize power and performance by using design-time traffic management techniques.
Improving NoC power efficiency and performance is critical for AI chips where inter-core communication is a major factor. Exploiting predictable traffic patterns can lead to more energy-efficient and faster AI hardware.
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Score 55
Source Type arxiv
Reposts 0
Topic Quality 49
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